1. Field of the Invention
The present invention relates to a circuit for testing frequency dividers.
2. Description of the Related Art
In a prior art frequency divider tester, as illustrated in FIG. 1, the frequency of an oscillator 1 is divided by a reference single-ratio frequency divider 2. The output of frequency divider 2 feeds a frame generator 4 to supply a NAND gate 5 with a frame pulse which defines a predetermined period of time, called reference frame. A single-ratio frequency divider 3 is the circuit that is under test. This frequency divider, having the same frequency dividing ratio as that of the reference frequency divider, is connected between the oscillator and the NAND gate. The output pulses of the under-test frequency divider, which are produced during a reference frame, are detected by the NAND gate and their binary count value is determined by a binary counter 6 and compared in a digital comparator 7 with a reference binary value manually established by an array of switches 8. The result of the test is obtained by checking the output of the comparator. When the frequency divider under test is functioning properly, the comparator inputs are of equal value and a high-level output is produced by the comparator. Otherwise, the comparator output is low.
However, one disadvantage of the prior art is that, if the frequency divider under test has more than one frequency dividing ratio, it is necessary to provide as many reference single-ratio frequency dividers as there are frequency dividing ratios. Another disadvantage is that since the oscillator is directly connected to both frequency dividers, instability results when it is energized during start-up. In addition, if there is a timing difference between both frequency dividers, the edges of the waveforms produced by the frequency divider under test and the frame generator do not coincide with each other. As a result, the output waveform of the NAND gate is not precise, causing a false output from the binary counter.